As electronic memories become smaller and denser, a memory array in an electronic memory has increased sensitivity to defects and noises. One such noise that can affect functionality of the electronic memories is random telegraph noise (RTN) that is caused by trapping and de-trapping of individual carriers due to active traps in gate oxide of memory cell transistors in the memory array. RTN brings about variations in threshold voltages of transistors in the memory cell. Such variations cause random failures in the memory cell leading to value of the memory cell being flipped. The random failures occur during read operations, write operations, or when the memory cell is in an idle state. Further, occurrence probability of the random failures due to RTN increases at low voltages and high temperatures.
Hence, there is a need for testing such random failures using an appropriate test algorithm with different testing conditions.